01Pre-silicon RTL verification and testbench development
02UVM-based functional verification strategies
03Coverage analysis and regression automation
04FPGA prototyping and emulation environments
05Firmware-assisted silicon validation
06Post-silicon bring-up and hardware debug
07Signal integrity and high-speed interface validation
08Performance characterization and stress testing
09Arm Cortex-A / M / R + NPU board bring-up — measured deterministic inter-processor messaging on the reference board (~88 µs round-trip floor, zero message loss) and from-scratch Arm Ethos-U NPU enablement
07Linux, RTOS, and bare-metal coexistence under DECS — measured ~20% round-trip latency reduction from removing the RTOS on the control core (controlled same-board comparison)
07Safety-gated inference architecture — validating AI decisions against safety constraints before actuation (the DECS design center)
08Closed-loop, control-theoretic edge control (real-time sense–infer–act loops)
09From-scratch NPU enablement: Vela / Arm Ethos-U bring-up demonstrated from scratch at 0.35–0.46 ms per inference, plus eIQ Neutron, Neural-ART, C7x-MMA, and train-on-NVIDIA-GPU / deploy-to-Jetson-with-TensorRT targets
02Cross-platform GUI development (Qt / embedded Linux / Windows)
03Real-time monitoring and control interfaces
04Hardware-accelerated graphics integration
05Multi-display and touch interface support
06Performance optimization and system integration
07Real-time system-monitor HMI demonstrated on the reference board — touch-driven, hardware-accelerated, resolution-independent, running over Wayland (coexisting with the vendor HMI), direct DRM/KMS, or serial, and driving a live on-device latency probe
