Technology

The core platform technologies inside DECS — secure, deterministic, and scalable edge systems.

Secure Boot & Root of Trust→

Hardware-anchored trust chain from first instruction.

Platform Architecture

01Hardware Root of Trust architecture (eFuse, TPM, HSM, secure elements)

02Chain-of-trust implementation from BootROM through OS

03Cryptographic image signing and verification (RSA/ECC/SHA-2/3)

04Measured boot and attestation support

05Anti-rollback protection and secure version management

06Secure firmware update frameworks (OTA-ready)

07Key management and secure provisioning workflows

08Trusted execution environment (TEE) integration

Edge AI Secure Kernel→

Protected runtime foundation for AI at the edge.

Architecture Highlights

01Deterministic real-time scheduling for AI inference workloads

02Secure execution isolation and memory protection

03Hardware acceleration integration (NPU / GPU / DSP)

04Lightweight, resource-optimized runtime for edge deployment

05Safety-gated inference: designed to validate AI decisions against safety constraints before actuation

06From-scratch NPU enablement — Arm Ethos-U person-detection demonstrated at 0.35–0.46 ms per inference (~2,900 inferences/s) on the reference board

Deterministic Runtime Architecture→

Predictable execution behavior under real-world load.

Architecture Highlights

01Deterministic scheduling and bounded-latency execution

02Memory isolation and partitioned resource management

03Multi-core orchestration (SMP / AMP) with workload separation

04Performance monitoring and real-time system diagnostics

05Bounded, closed-loop execution model (sense, infer, decide, act)

06Measured latency distributions (p50 ~106 µs idle at 96 B, ~136 µs under concurrent NPU-plus-GUI load; p90 ~137 µs idle, ~193 µs loaded; p99 ~157 µs idle, ~385 µs loaded), with zero errors and zero drops across 30,000+ messages

Safety-Oriented Hypervisor→

Partitioned virtualization aligned to safety goals.

Platform Capabilities

01Certification alignment up to ISO 26262 (ASIL D) and DO-178C objectives

02Deterministic real-time partition scheduling

03Hardware-assisted virtualization (ARM virtualization extensions)

04Static partitioning that isolates the AI inference path from the real-time control path

05Strong memory isolation and fault containment

06Mixed-criticality workload separation (safety, control, AI, HMI)

07Secure boot integration and trusted execution support

Real-Time AI Acceleration Framework→

Low-latency AI execution path optimization.

Platform Capabilities

01Real-time AI workload scheduling with bounded latency

02Hardware accelerator integration (NPU / GPU / DSP) with optimized data paths

03Low-latency inference pipelines and memory-efficient execution

04From-scratch NPU enablement, including the Vela model pipeline, on-device runtime, and live inference dashboard

05Deployment targets: Arm Ethos-U, Neural-ART, eIQ Neutron, C7x-MMA DSP, FPGA DPU / AI Engines, and NVIDIA Jetson (TensorRT)